Recently, I had a (trivial) idea:
If I got that right, in protected mode, an x86_64 processor needs four (!!!) dereferencings for every memory reference the code makes. With one more, more RAM would be needed for the tables, but it would also be possible to have pagesize=wordsize. This would be especially interesting in the scope of lazy evaluation, when you could use pagefaults as a mechanism for triggering calculations. And one could implement fine-grained deduplication and copy-on-write for the heap space of usermode processes.
This would be pretty optimal for functional programs, and would only add one more level of dereferencing.
Just for my personal interest, would such an extension to x86 (or some other architecture) be reasonable? What would be the disadvantages? I am interested in any kind of qualified (or semi-qualified) comment.